The physical implementation of integrated circuit (IC) designs developed using Hardware Description Languages (HDL) such as Verilog and VHDL, is a tedious, effort and time-intensive process. The main IC design development steps are typically high-level architecture definition, register transfer level (RTL) code development, functional verification, synthesis and timing optimization, floorplanning, cell placement and timing optimization, routing and final verification. If a design is unable to successfully complete routing it is considered a routing congestion failure.
The design team attempts to resolve a routing congestion failure using a combination of methods: (i) decrease the design utilization, i.e., implement the block with larger silicon area; (ii) change the floorplan to allocate more area for the affected block, often causing a sub-optimal floorplan and degradation in design performance; and (iii) change the design itself by changing the design's HDL description. Each of the methods creates a significant loss in terms of increased time to design implementation completion, time to market for the finished product, larger silicon area, reduced performance and clock frequency, risk of not fitting into chosen chip package, and higher development cost.
Given the high cost of resolving routing congestion, a method to predict routing congestion at the pre-floorplan stage of design development is very valuable to design development teams. By predicting routing congestion early in the development cycle, the development team can take corrective steps before going to physical implementation, and hence significantly reduce risk to timely completion and overall cost of development.